Avicena, a trailblazing company headquartered in Sunnyvale, California, is marking a significant technological advancement by showcasing the world’s smallest 1Tbps optical transceiver at the SuperComputing Conference 2023 in Denver, Colorado. This groundbreaking development, part of Avicena’s LightBundleTM multi-Tbps chip-to-chip interconnect technology, is set to redefine the landscape of optical transceivers.
In an era where artificial intelligence (AI) and large language models (LLMs) like ChatGPT demand increasingly powerful computing and memory capabilities, Avicena’s innovation couldn’t be more timely. The pressing need for high-density, low-power interconnects between Graphics Processing Units (GPUs) and high-bandwidth memory (HBM) modules is acute. Currently, the limitations of GPU-memory electrical interconnects necessitate the co-packaging of HBM modules with GPUs, a constraint that future HBM generations aim to overcome with IC shoreline densities potentially reaching or exceeding 10Tbps/mm.
Conventional optical interconnects, such as those based on Vertical-Cavity Surface-Emitting Lasers (VCSELs) or Silicon Photonics (SiPh), although promising in extending interconnect reach, fall short in meeting the holistic requirements of size, bandwidth density, power, latency, operating temperature, and cost. Avicena’s microLED-based LightBundle interconnects stand out in this regard, offering superior bandwidth density, smaller size, lower power and latency, and very low costs, especially in short reach interconnects of less than 10 meters.
Bardia Pezeshki, Founder and CEO of Avicena, emphasizes the company’s commitment to pushing the boundaries of optical interconnect technology. He points out that while Silicon Photonics solutions are the go-to for AI clusters, Avicena’s LED-based solution excels in short reach interconnects, boasting compact size, higher bandwidth density, lower power and latency, and a temperature tolerance of up to 150°C.
Avicena’s technological prowess is backed by significant investment from industry giants, including the Samsung Catalyst Fund, Cerberus Capital Management, Clear Ventures, and Micron Ventures. The support from these key investors underscores the potential impact and applicability of Avicena’s technology in the rapidly evolving AI and machine learning sectors.
Marco Chisari, head of the Samsung Semiconductor Innovation Center, lauds the potential of optical interconnect technology, particularly Avicena’s LightBundle interconnects, in enhancing chip-to-chip and inter-rack performance. He points to the roadmap of multi-Tbps capacity and sub-pJ/bit power efficiency as a catalyst for the next era of AI innovation, setting the stage for more capable AI models and a broad spectrum of AI applications that will significantly influence the future.
Avicena’s LightBundleTM interconnect architecture, featuring arrays of GaN microLEDs that leverage the microLED display ecosystem, is a radical departure from traditional approaches. This architecture enables dense, low-power IO over the entire area of the IC, achieving unprecedented shoreline densities. Each microLED array connects to a multi-core fiber cable, which then links to a matching array of CMOS-compatible photodetectors (PDs).
Rob Kalman, co-founder and CTO of Avicena, elaborates on the company’s achievements in microLED transmission, highlighting the progress from a test ASIC in a 130nm CMOS process to their latest ASIC, boasting over 300 lanes with an aggregate bandwidth of over 1Tbps bi-directional at 4Gbps per lane. This ASIC, measuring less than 12mm2, encompasses a full transceiver including optical Tx and Rx arrays and a high-speed parallel electrical interface, among other features. With key ASIC functionality verified, Avicena is now focused on yield improvements to scale up manufacturing.
The modular LightBundle platform is not only scalable to interconnects with tens of Tbps and a shoreline density exceeding 10Tbps/mm but is also process-agnostic, allowing integration onto a variety of IC process nodes. The compact size, high density, low power, and low latency of LightBundle make it ideal for high-density chiplet interfaces like UCIe, OpenHBI, and BoW. It also significantly extends the reach of existing compute interconnects such as PCIe/CXL, and HBM/DDR/GDDR memory links.
Avicena’s presence at SC23, where it will showcase its LightBundle interconnect technology at Booth #1791, signifies a monumental step in the evolution of networking and computing technology. The company’s innovations not only pave the way for enhanced system performance and throughput but also contribute to reducing the energy impact on our planet. As we move towards more advanced and energy-efficient computing infrastructures, Avicena’s LightBundle technology is poised to play a crucial role in this transformative journey.
